MicroNanoSpain

Chip design education: AI, open-source tools and talent in Barcelona

MicroNanoSpain • • 10 min read
Chip design education: AI, open-source tools and talent in Barcelona

On 29 October 2026, MicroNanoSpain, in collaboration with the Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC), will host the One-Day Chip Design Education Workshop in Barcelona. The event will bring together educators, researchers, students and companies to address one question: how should we educate the people who will design the next generation of semiconductors?

Attendance will be free with prior registration, with in-person participation and livestream viewing. The event will combine short presentations, roundtable discussions and opportunities for conversation around four themes: education pathways, design tools, the impact of artificial intelligence, and the relationship between academia and industry.

Explore the programme and register for the MicroNanoSpain workshop.

What is chip design, and what does a designer do?

But first of all, what does it mean to design a chip? Designing a chip is you. Well, more precisely, designing a chip means finding ways to connect and organise its different components. We can compare it to a city: tiny wires made of copper, gold or other materials act as “streets”, allowing “people” to move around. In the case of chips, these are the small electrical signals that flow between the components making up the chip, which would be the buildings in our city.

Design is an art that goes beyond visual appearance, as it must take account of other aspects such as speed, the distance between circuits, the capabilities of different materials, power consumption, space… There are many variables that can cause something to go wrong, potentially preventing the device we want to build from working when it is manufactured.

Because of its importance to how the chip works, design does not stop at drawing a plan showing where each building and road will be located within the chip: its behaviour must also be checked. This is done using, among other resources, electronic design automation tools —EDA—. Simulation makes it possible to study how a circuit will respond under different conditions and to detect errors before a physical device exists. Learning to design therefore involves not only creating a solution, but also verifying it and interpreting its results, as well as ensuring that these designs are useful in the contexts in which the components will ultimately be used. Designing a chip for a car, for example, will not be the same as designing a chip for a spacecraft.

The importance of chip design leads us to seek an answer to a question that will help us understand the future of this discipline, this art: what should future engineers learn, and how can we bring their education closer to industry practice?

To open the day and introduce the event, Rafael Gomà, Senior Research Engineer at the Barcelona Supercomputing Center (BSC), and Antonio Rubio, Emeritus Professor at the Universitat Politècnica de Catalunya (UPC), will deliver the institutional welcome and set out the objectives for the day.

What to study to become a chip designer: from undergraduate to master’s studies and beyond

The first session will address the present and future of education pathways. Participants will share experiences of the content being taught, the capabilities universities are developing, and the challenges they face when preparing new professionals. This session will be led by Antonio Rubio.

Chips design. The importance of trainings in the semiconductor industry
Source: Barcelona Supercomputing Center https://www.bsc.es/es/noticias/noticias-del-bsc/el-barcelona-zettascale-lab-avanza-hacia-la-soberan%C3%ADa-tecnol%C3%B3gica-europea-con-la-validaci%C3%B3n-del-chip

Roger Espasa from Semidynamics will present the proposal for a degree in Chip Design. Jordi Carrabina from the Universitat Autònoma de Barcelona will discuss the journey from master’s to undergraduate studies. Armando Astarloa, from the Bilbao School of Engineering, will share experiences, achievements and challenges in strengthening its design capabilities.

The discussion will also broaden its focus to other stages and areas of knowledge within microelectronics. Guillermo Carpintero from Universidad Carlos III de Madrid will introduce the back-end, focusing in his presentation on assembly and packaging. Vicente Jiménez from UPC will address challenges in electronics education; Carlos Sampedro from the University of Granada will connect device-level education with chip design; and Armand Estévez from ICFO will explore the skills the next generation of designers will need beyond electronics.

The session will offer different starting points for discussing a shared question: how to build education pathways that connect fundamentals with specialisation and professional needs.

Chip design with free software: tools to bring silicon into the classroom

After course content, another question will follow: which tools do we learn with, and how do we move from learning to implementation? To guide the conversation, we will be joined by Teresa Cervero, Leading Research Engineer at the Barcelona Supercomputing Center (BSC), and Antonio Núñez, Professor and Emeritus Professor at the Universidad de Las Palmas de Gran Canaria (ULPGC) and founder of the University Institute of Applied Microelectronics (IUMA).

The second session will explore the opportunities that open-source hardware and software offer for teaching. Matt Venn from Tiny Tapeout will discuss access to silicon through open-source tools and multi-project chips. Andrés Otero from Universidad Politécnica de Madrid will address the potential of open-source hardware and software for microelectronics teaching in Spain, while Francesc Moll-Echeto from UPC will present how to design chips using free software.

The session will continue with Óscar Plata from the University of Málaga and his perspective on digital design education, from describing logic to integrating a system on a chip. Enrique Márquez, also from the University of Málaga, will discuss the use of free software to design microwave integrated circuits. Sergio Gómez from UPC will focus on the leap from learning to implementation.

The educational interest lies not simply in knowing the names of tools, but in discussing how to incorporate them into teaching so that students understand the decisions they make and the results they obtain.

Artificial intelligence in chip design: what to teach and what engineers should supervise

Artificial intelligence will be the focus of the third session, with an important distinction: the discussion will not be limited to chips that run AI, but will address how to use AI to teach microelectronics and develop designs. The planned presentations connect teaching practice with analogue design, human responsibility and physical chip design. On this occasion, the session will be led by Rafael Gomà.

A recent industry announcement illustrates this context: on 30 September 2026, Synopsys and OpenAI announced a collaboration to develop GPT-Synopsys, a model specialised in using EDA tools. The project envisages agents carrying out tasks and interpreting results, with engineers reviewing their work. Such initiatives highlight the relevance of an educational question: what knowledge does a person need to evaluate the work of these tools?

At the workshop, José Flich from Universitat Politècnica de València will share experiences of AI in teaching and in computer architecture courses using RISC-V. Antonio José Acosta from the University of Seville and IMSE-CNM will address microelectronics education with AI. José Roque —Roc— Berenguer from TECNUN will ask, from the perspective of analogue design, “Will we still need designers?” Miquel Aberti, a researcher at BSC, will explain how design engineers’ skills need to change in response to artificial intelligence.

Supervision will also play a central role. Oscar Alonso from the University of Barcelona will cover its integrated circuit design pathway. Eugenio Villar from the University of Cantabria will address the relationship between artificial intelligence and human responsibility. Christian Fabiano from Cisco will discuss AI as a physical chip design engineer, including its usefulness and the risks of using it without supervision. These presentations will open a discussion on how to take advantage of new capabilities without separating the use of a tool from an understanding of the circuit.

Academia and industry: connecting education with work in semiconductors

The final session will bring together academic and industry perspectives to exchange experiences, needs and opportunities for collaboration. Our final session leader will be Oriol Recasens Benito, Secretary and Head of the Department of Science and Innovation at Barcelona City Council.

Vincent Casillas from SiPearl will share the company’s perspective on connecting with academia. Paula López from Universidade de Santiago de Compostela and CiTIUS will present remotely, addressing why academia and industry need each other more than ever. Ricardo Martinez from Openchip will offer his perspective on chip design and talent in the AI era. Sergi Claramunt and Jemish Parmar from IDEADED will present possible solutions to close education and training gaps for the next generations of semiconductor professionals.

The session will also include a teaching experience: Fernando Rincón from Universidad de Castilla-La Mancha will present eHardware, a platform providing remote access to field-programmable gate arrays —FPGAs— for hardware design teaching.

Connecting knowledge, education and business needs is part of MicroNanoSpain’s work. At this event, that connection will take the form of a space where companies can communicate their needs and educational institutions can share and compare their approaches.

Closing session

To bring the event to a close, Roger Costa, Senior Semiconductor Projects Consultant at ACCIÓ and coordinator of the Government of Catalonia’s Semiconductor Strategy, will lead the closing session. He will present a summary of the day’s main points, the key conclusions reached across the discussions, and the next steps towards answering our original question: how should we educate the people who will design the next generation of semiconductors?

BSC presents Sargantana, the new generation of the first open-source chips designed in Spain
Source: Barcelona Supercomputing Center https://www.bsc.es/es/noticias/noticias-del-bsc/el-bsc-presenta-sargantana-la-nueva-generaci%C3%B3n-de-los-primeros-chips-de-c%C3%B3digo-abierto-dise%C3%B1ados-en

A day to exchange experiences and meet other participants

If you are a student, the event will allow you to hear how universities and companies approach education pathways and changes in chip design. If you teach or conduct research, you will find experiences of course content, tools and methodologies to discuss. If you work in a company, you will be able to join the conversation about the capabilities that talent in the sector should develop.

The format will combine ten-minute presentations with roundtable discussions and open dialogue. Coffee and lunch breaks will provide opportunities to continue conversations and explore shared interests.

The aim will be to gather conclusions that can serve as a basis for wider initiatives, including a possible international event in 2027.

Workshop in Barcelona on 29 October: free registration

The One-Day Chip Design Education Workshop will take place on Thursday, 29 October 2026, from 09:00 to 17:45, in the Sala Màster, Building A3, UPC Campus Nord, at Carrer de Jordi Girona, 1-3, Barcelona. Accreditation will begin at 09:00, and the programme will open at 09:30.

Attendance will be free with prior registration, with in-person participation and livestream viewing. The event will be conducted in Spanish, although presentations in English are accepted.

Bring your questions about education, design tools, artificial intelligence or university–industry collaboration. The event is intended to bring these issues into a shared conversation with people who teach, research and develop technology.

View the updated programme and practical information, and reserve your place.

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The MicroNanoSpain project has received funding from the Chips Joint Undertaking (CHIPS JU) under grant agreement No 101217813, with support from the European Union and national funding from the Ministerio para la Transformación Digital y de la Función Pública under Grant No CJU-010100-2025-5

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