Attendance will be free with prior registration, with in-person participation and livestream viewing. The event will combine short presentations, roundtable discussions and opportunities for conversation around four themes: education pathways, design tools, the impact of artificial intelligence, and the relationship between academia and industry.

Explore the programme and register for the MicroNanoSpain workshop.

What is chip design, and what does a designer do?

But first of all, what does it mean to design a chip? Designing a chip is you. Well, more precisely, designing a chip means finding ways to connect and organise its different components. We can compare it to a city: tiny wires made of copper, gold or other materials act as “streets”, allowing “people” to move around. In the case of chips, these are the small electrical signals that flow between the components making up the chip, which would be the buildings in our city.

Design is an art that goes beyond visual appearance, as it must take account of other aspects such as speed, the distance between circuits, the capabilities of different materials, power consumption, space… There are many variables that can cause something to go wrong, potentially preventing the device we want to build from working when it is manufactured.

Because of its importance to how the chip works, design does not stop at drawing a plan showing where each building and road will be located within the chip: its behaviour must also be checked. This is done using, among other resources, electronic design automation tools —EDA—. Simulation makes it possible to study how a circuit will respond under different conditions and to detect errors before a physical device exists. Learning to design therefore involves not only creating a solution, but also verifying it and interpreting its results, as well as ensuring that these designs are useful in the contexts in which the components will ultimately be used. Designing a chip for a car, for example, will not be the same as designing a chip for a spacecraft.

The importance of chip design leads us to seek an answer to a question that will help us understand the future of this discipline, this art: what should future engineers learn, and how can we bring their education closer to industry practice?

To open the day and introduce the event, Rafael Gomà, Senior Research Engineer at the Barcelona Supercomputing Center (BSC), and Antonio Rubio, Emeritus Professor at the Universitat Politècnica de Catalunya (UPC), will deliver the institutional welcome and set out the objectives for the day.

What to study to become a chip designer: from undergraduate to master’s studies and beyond

The first session will address the present and future of education pathways. Participants will share experiences of the content being taught, the capabilities universities are developing, and the challenges they face when preparing new professionals. This session will be led by Antonio Rubio.

Roger Espasa from Semidynamics will present the proposal for a degree in Chip Design. Jordi Carrabina from the Universitat Autònoma de Barcelona will discuss the journey from master’s to undergraduate studies. Armando Astarloa, from the Bilbao School of Engineering, will share experiences, achievements and challenges in strengthening its design capabilities.

The discussion will also broaden its focus to other stages and areas of knowledge within microelectronics. Guillermo Carpintero from Universidad Carlos III de Madrid will introduce the back-end, focusing in his presentation on assembly and packaging. Vicente Jiménez from UPC will address challenges in electronics education; Carlos Sampedro from the University of Granada will connect device-level education with chip design; and Armand Estévez from ICFO will explore the skills the next generation of designers will need beyond electronics.

The session will offer different starting points for discussing a shared question: how to build education pathways that connect fundamentals with specialisation and professional needs.

Chip design with free software: tools to bring silicon into the classroom

After course content, another question will follow: which tools do we learn with, and how do we move from learning to implementation? To guide the conversation, we will be joined by Teresa Cervero, Leading Research Engineer at the Barcelona Supercomputing Center (BSC), and Antonio Núñez, Professor and Emeritus Professor at the Universidad de Las Palmas de Gran Canaria (ULPGC) and founder of the University Institute of Applied Microelectronics (IUMA).

The second session will explore the opportunities that open-source hardware and software offer for teaching. Matt Venn from Tiny Tapeout will discuss access to silicon through open-source tools and multi-project chips. Andrés Otero from Universidad Politécnica de Madrid will address the potential of open-source hardware and software for microelectronics teaching in Spain, while Francesc Moll-Echeto from UPC will present how to design chips using free software.

The session will continue with Óscar Plata from the University of Málaga and his perspective on digital design education, from describing logic to integrating a system on a chip. Enrique Márquez, also from the University of Málaga, will discuss the use of free software to design microwave integrated circuits. Sergio Gómez from UPC will focus on the leap from learning to implementation.

The educational interest lies not simply in knowing the names of tools, but in discussing how to incorporate them into teaching so that students understand the decisions they make and the results they obtain.

Artificial intelligence in chip design: what to teach and what engineers should supervise

Artificial intelligence will be the focus of the third session, with an important distinction: the discussion will not be limited to chips that run AI, but will address how to use AI to teach microelectronics and develop designs. The planned presentations connect teaching practice with analogue design, human responsibility and physical chip design. On this occasion, the session will be led by Rafael Gomà.

A recent industry announcement illustrates this context: on 30 September 2026, Synopsys and OpenAI announced a collaboration to develop GPT-Synopsys, a model specialised in using EDA tools. The project envisages agents carrying out tasks and interpreting results, with engineers reviewing their work. Such initiatives highlight the relevance of an educational question: what knowledge does a person need to evaluate the work of these tools?

At the workshop, José Flich from Universitat Politècnica de València will share experiences of AI in teaching and in computer architecture courses using RISC-V. Antonio José Acosta from the University of Seville and IMSE-CNM will address microelectronics education with AI. José Roque —Roc— Berenguer from TECNUN will ask, from the perspective of analogue design, “Will we still need designers?” Miquel Aberti, a researcher at BSC, will explain how design engineers’ skills need to change in response to artificial intelligence.

Supervision will also play a central role. Oscar Alonso from the University of Barcelona will cover its integrated circuit design pathway. Eugenio Villar from the University of Cantabria will address the relationship between artificial intelligence and human responsibility. Christian Fabiano from Cisco will discuss AI as a physical chip design engineer, including its usefulness and the risks of using it without supervision. These presentations will open a discussion on how to take advantage of new capabilities without separating the use of a tool from an understanding of the circuit.

Academia and industry: connecting education with work in semiconductors

The final session will bring together academic and industry perspectives to exchange experiences, needs and opportunities for collaboration. Our final session leader will be Oriol Recasens Benito, Secretary and Head of the Department of Science and Innovation at Barcelona City Council.

Vincent Casillas from SiPearl will share the company’s perspective on connecting with academia. Paula López from Universidade de Santiago de Compostela and CiTIUS will present remotely, addressing why academia and industry need each other more than ever. Ricardo Martinez from Openchip will offer his perspective on chip design and talent in the AI era. Sergi Claramunt and Jemish Parmar from IDEADED will present possible solutions to close education and training gaps for the next generations of semiconductor professionals.

The session will also include a teaching experience: Fernando Rincón from Universidad de Castilla-La Mancha will present eHardware, a platform providing remote access to field-programmable gate arrays —FPGAs— for hardware design teaching.

Connecting knowledge, education and business needs is part of MicroNanoSpain’s work. At this event, that connection will take the form of a space where companies can communicate their needs and educational institutions can share and compare their approaches.

Closing session

To bring the event to a close, Roger Costa, Senior Semiconductor Projects Consultant at ACCIÓ and coordinator of the Government of Catalonia’s Semiconductor Strategy, will lead the closing session. He will present a summary of the day’s main points, the key conclusions reached across the discussions, and the next steps towards answering our original question: how should we educate the people who will design the next generation of semiconductors?

A day to exchange experiences and meet other participants

If you are a student, the event will allow you to hear how universities and companies approach education pathways and changes in chip design. If you teach or conduct research, you will find experiences of course content, tools and methodologies to discuss. If you work in a company, you will be able to join the conversation about the capabilities that talent in the sector should develop.

The format will combine ten-minute presentations with roundtable discussions and open dialogue. Coffee and lunch breaks will provide opportunities to continue conversations and explore shared interests.

The aim will be to gather conclusions that can serve as a basis for wider initiatives, including a possible international event in 2027.

Workshop in Barcelona on 29 October: free registration

The One-Day Chip Design Education Workshop will take place on Thursday, 29 October 2026, from 09:00 to 17:45, in the Sala Màster, Building A3, UPC Campus Nord, at Carrer de Jordi Girona, 1-3, Barcelona. Accreditation will begin at 09:00, and the programme will open at 09:30.

Attendance will be free with prior registration, with in-person participation and livestream viewing. The event will be conducted in Spanish, although presentations in English are accepted.

Bring your questions about education, design tools, artificial intelligence or university–industry collaboration. The event is intended to bring these issues into a shared conversation with people who teach, research and develop technology.

View the updated programme and practical information, and reserve your place.

The second edition of the forum, organised by AESEMI within the MicroNanoSpain ecosystem, took place in the Europa Room of the Official College of Industrial Engineers of Madrid (COIIM). The programme combined an overview of the sector, round-table discussions on investment and funding, company presentations and direct meetings between the different stakeholders in the ecosystem.

The objective was clear: to move beyond initial contacts towards concrete opportunities for investment, funding and collaboration.

Capital to help the semiconductor industry grow

Developing a project within the semiconductor ecosystem poses particular financial challenges. Development cycles can be long, many technologies require intensive research and validation phases and, depending on the project, scaling up may require infrastructure, manufacturing, prototyping or access to highly specialised capabilities.

For this reason, the II Semicon Investors Day brought together three particularly relevant groups in one place: startups and technology companies, private investors and public funding organisations.

The forum was more than a series of project presentations to potential investors. It provided a space for companies to better understand the investment criteria of private capital, learn about available public instruments and hold direct conversations with organisations that can support their growth.

A snapshot of Spain’s semiconductor ecosystem

The day began with an institutional welcome by Carlos Pardo, President of AESEMI, followed by a session examining the current state of Spain’s semiconductor ecosystem.

The session featured Alfonso Gabarrón, Managing Director of AESEMI, and Luis Fernández Ledesma, Director of Strategic Alliances and Business Development at imec, who shared an illustrative figure: since 2020, one semiconductor company has been created each month in Spain.

This opening session set the context for the investment discussions that followed, outlining the capabilities already in place, where growth opportunities lie and what businesses need to progress from technological development to industrial consolidation.

Venture capital and deep tech: what do investors look for in semiconductors?

One of the central parts of the II Semicon Investors Day was the Venture Builder Capital round table, dedicated to the role of private capital in the growth of technology companies.

The session, moderated by Iñigo Martín of AESEMI’s Industrial Policy Committee, featured representatives from several investment organisations:

• Roberto Ranera, Partner at BEABLE CAPITAL.
• Javier Ulecia, Founding Partner at BULLNET CAPITAL.
• Fernando Aguirre, Founding Partner at HASTEN.
• José Marino García, Executive Director of Capitalisation at SETT.

Bringing together different investor profiles made it possible to address a fundamental question for deep-tech companies: what makes a technology project investable and how can a startup prepare to access capital?

In semiconductors, this discussion is particularly important because assessing a company may go far beyond traditional growth metrics. Intellectual property, the technical team, access to manufacturing, time to market, scalability, technological differentiation and potential applications may be decisive factors.

Public funding to turn innovation into industry

The second major financial session will be devoted to funding for innovation.

Moderated by Mercedes Lecea, Technology Transfer & Venture Builder Manager, the panel featured:

• David de la Torre, Digital Technologies Department at CDTI.
• Daniel Agudo, Director of Institutional Relations at ZABALA.
• Francisco Ignacio, Senior Programme Officer at the Chips Joint Undertaking.
• Paz Guzmán, Senior Economic Adviser at the European Investment Bank.

The panel’s composition made it possible to discuss different levels of funding, from national instruments to European mechanisms linked to innovation, technology and industry.

For companies in the ecosystem, understanding these instruments can be particularly useful. The growth of a technology company may be based on

investment rounds, grants, European programmes, innovation funding, loans and other instruments as part of a combined strategy.

Among its services, MicroNanoSpain specifically envisages support for entrepreneurship and innovation, including connections with investors, funding opportunities and mechanisms to bring companies and startups closer to resources within the semiconductor ecosystem.

Seven projects presented to investors and funders

The event also provided a dedicated space for companies in the sector to present their proposals directly.

The Elevator Pitch session featured technology projects approaching the semiconductor sector from different angles, with presentations by:

• LeapWave Technologies, represented by Alejandro Rivera Lavado, CTO and founder.
• BIOBEE semiconductors, with Javier Ramos, CEO.
• G2-Zero, with José Manuel Llorens, research adviser and founder.
• Deep Detection, with Alejandro Rueda Gómez, Chief Financial Officer.
• Ommatidia, with Inmaculada Uzquiano Camino, Financial Manager.
• SiCure, with Alejandro Espin, Project Manager.
• Energhius, with Daniel García Lesta, CEO and co-founder.

The speakers presented their technology, value proposition and needs. For the participating funds and organisations, the elevator pitch also provided a way to identify emerging projects and technologies in the Spanish ecosystem.

Matchmaking spaces and the launch of ChipNConnect

To round off the event, two spaces were made available to encourage networking. A general cocktail reception took place between 14:00 and 16:00, complemented by speed-dating sessions in private rooms.

This gave participants the opportunity to interact informally with companies and investors while also arranging specific meetings in rooms separate from the other attendees.

These interactions were supported by the presentation of ChipNConnect, the new networking tool provided by MicroNanoSpain. Attendees were able to try the beta version of this professional matchmaking platform linked to the ecosystem, create a profile, identify shared interests, match with other participants and facilitate subsequent meetings and conversations.

The app aims to overcome barriers at matchmaking events, such as not knowing attendees’ roles and companies, not finding the right moment to approach someone to suggest a meeting or, most importantly when deciding whom to talk to, not knowing what they are looking for and what they can offer. The information users provide in their profiles makes it easier to find suitable contacts.

The same application also enabled users to schedule meetings during the event (in the private rooms) or at a later date (online, for example).

Connecting technology, funding and growth

Building a consolidated semiconductor industry does not depend solely on scientific and technological knowledge. It also requires mechanisms that can turn that knowledge into companies, products, intellectual property and industrial capacity.

This means connecting research more effectively with the market, while also helping technology projects find the right capital, funding, partners and support at each stage of growth.

The II Semicon Investors Day addresses precisely this meeting point.

Over the course of one day, companies developing technology, investors seeking new opportunities and organisations managing support instruments shared the same space.

And in a sector where taking an innovation from the laboratory to the market can be particularly complex, creating those connections may be just as important as developing the technology itself.

The event will gather companies, universities, technology centres, R&D centres and public bodies with the aim of connecting projects, talent, technological capabilities and specialised infrastructures. The day seeks to foster new collaborations and contribute to the development of microelectronics and semiconductors in Spain.

A meeting to boost the chip industry

The semiconductor industry has become a strategic sector for technological, industrial and economic competitiveness. Chips are present in areas such as automotive, artificial intelligence, defence, telecommunications, healthcare, energy and aerospace.

In this context, the 1st Matchmaking Day was created to facilitate connections between the main players in the sector and strengthen collaboration between research, industry and institutions.

Event agenda

The programme will begin with the reception of attendees and the institutional welcome by Diego Crescente, Director General of EOI, followed by the opening address by Carlos Pardo, CEO and Co-founder of KDPOF and President of AESEMI.

This will be followed by the institutional roundtable “Funding and calls for the semiconductor ecosystem 2026”, with the participation of representatives from madri+d, AESEMI, Universidad Politécnica de Madrid and CSIC-CAR.

The day will continue with different speech sessions led by companies, research centres and organisations linked to the sector, as well as networking spaces to facilitate contact between attendees.

In the afternoon, thematic sessions will be held on areas such as neuromorphic computing, aerospace and defence, and quantum technology.

Registration for the 1st Matchmaking Day

The 1st Matchmaking Day is aimed at all stakeholders interested in connecting with those driving the chip industry in Spain.

Sign up and participate in the MicronanoSpain I Matchmaking Day.

Where it takes place

The 1st Matchmaking Day will take place on Tuesday, 30 June, from 10:00 to 17:30, at the Escuela de Organización Industrial (EOI), Av. de Gregorio del Amo, 6, Moncloa-Aravaca, 28040 Madrid.

The event provides a practical environment where participants can refine their communication skills, receive expert feedback, and enhance their proposals before presenting them in real-world settings. This initiative aligns with MicroNanoSpain’s mission to promote knowledge transfer and strengthen the capabilities of the national and European semiconductor ecosystem.

Through activities like this, MNS continues to position itself as a key hub connecting research, industry, and talent, driving the development of innovative solutions in the micro- and nanoelectronics field.